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    A Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications

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    ReaZanabria_ku_0099M_11339_DATA_1.pdf (2.751Mb)
    Issue Date
    2011-03-31
    Author
    Rea Zanabria, Gino
    Publisher
    University of Kansas
    Format
    116 pages
    Type
    Thesis
    Degree Level
    M.S.
    Discipline
    Electrical Engineering & Computer Science
    Rights
    This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.
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    Abstract
    This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed.
    URI
    http://hdl.handle.net/1808/7644
    Collections
    • Engineering Dissertations and Theses [1055]
    • Theses [3827]

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    785-864-8983
    KU Libraries
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    785-864-8983

    KU Libraries
    1425 Jayhawk Blvd
    Lawrence, KS 66045
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    Contact KU ScholarWorks
    785-864-8983
    KU Libraries
    1425 Jayhawk Blvd
    Lawrence, KS 66045
    785-864-8983

    KU Libraries
    1425 Jayhawk Blvd
    Lawrence, KS 66045
    Image Credits
     

     

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