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dc.contributor.advisorPerrins, Erik
dc.contributor.authorRea Zanabria, Gino
dc.date.accessioned2011-06-21T16:35:34Z
dc.date.available2011-06-21T16:35:34Z
dc.date.issued2011-03-31
dc.date.submitted2011
dc.identifier.otherhttp://dissertations.umi.com/ku:11339
dc.identifier.urihttp://hdl.handle.net/1808/7644
dc.description.abstractThis thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed.
dc.format.extent116 pages
dc.language.isoen
dc.publisherUniversity of Kansas
dc.rightsThis item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.
dc.subjectElectrical engineering
dc.subjectDemodulator
dc.subjectFec
dc.subjectFpga
dc.subjectHardware
dc.subjectImplementation
dc.subjectSoqpsk-tg
dc.titleA Hardware Implementation of a Coherent SOQPSK-TG Demodulator for FEC Applications
dc.typeThesis
dc.contributor.cmtememberBlunt, Shannon
dc.contributor.cmtememberGill, Andrew
dc.thesis.degreeDisciplineElectrical Engineering & Computer Science
dc.thesis.degreeLevelM.S.
kusw.oastatusna
kusw.oapolicyThis item does not meet KU Open Access policy criteria.
kusw.bibid7642815
dc.rights.accessrightsopenAccess


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