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dc.contributor.advisorAndrews, David
dc.contributor.advisorAlexander, Perry
dc.contributor.authorOrtiz, Jorge
dc.date.accessioned2010-01-07T23:40:40Z
dc.date.available2010-01-07T23:40:40Z
dc.date.issued2009-12-22
dc.date.submitted2009
dc.identifier.otherhttp://dissertations.umi.com/ku:10672
dc.identifier.urihttp://hdl.handle.net/1808/5670
dc.description.abstractThe accelerated adoption of reconfigurable computing foreshadows a computational paradigm shift, aimed at fulfilling the need of customizable yet high-performance flexible hardware. Reconfigurable computing fulfills this need by allowing the physical resources of a chip to be adapted to the computational requirements of a specific program, thus achieving higher levels of computing performance. This dissertation evaluates the area requirements for reconfigurable processing, an important yet often disregarded assessment for partial reconfiguration. Common reconfigurable computing approaches today attempt to create custom circuitry in static co-processor accelerators. We instead focused on a new approach that synthesized semi-custom general-purpose processor cores. Each superscalar processor core's execution units can be customized for a particular application, yet the processor retains its standard microprocessor interface. We analyzed the area consumption for these computational components by studying the synthesis requirements of different processor configurations. This area/performance assessment aids designers when constraining processing elements in a fixed-size area slot, a requirement for modern partial reconfiguration approaches. Our results provide a more deterministic evaluation of performance density, hence making the area cost analysis less ambiguous when optimizing dynamic systems for coarse-grained parallelism. The results obtained showed that even though performance density decreases with processor complexity, the additional area still provides a positive contribution to the aggregate parallel processing performance. This evaluation of parallel execution density contributes to ongoing efforts in the field of reconfigurable computing by providing a baseline for area/performance trade-offs for partial reconfiguration and multi-processor systems.
dc.format.extent144 pages
dc.language.isoEN
dc.publisherUniversity of Kansas
dc.rightsThis item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.
dc.subjectElectronics and electrical engineering
dc.subjectComputer engineering
dc.subjectFpga
dc.subjectProcessor
dc.subjectReconfigurable
dc.subjectSuperscalar
dc.subjectSynthesis
dc.titleSynthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors
dc.typeDissertation
dc.contributor.cmtememberAgah, Arvin
dc.contributor.cmtememberChakrabarti, Swapan
dc.contributor.cmtememberSterbenz, James
dc.contributor.cmtememberMcClure, Kirk
dc.thesis.degreeDisciplineElectrical Engineering & Computer Science
dc.thesis.degreeLevelPh.D.
kusw.oastatusna
kusw.oapolicyThis item does not meet KU Open Access policy criteria.
dc.rights.accessrightsopenAccess


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