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    Synthesis Techniques for Semi-Custom Dynamically Reconfigurable Superscalar Processors

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    Ortiz_ku_0099D_10672_DATA_1.pdf (3.178Mb)
    Issue Date
    2009-12-22
    Author
    Ortiz, Jorge
    Publisher
    University of Kansas
    Format
    144 pages
    Type
    Dissertation
    Degree Level
    Ph.D.
    Discipline
    Electrical Engineering & Computer Science
    Rights
    This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.
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    Abstract
    The accelerated adoption of reconfigurable computing foreshadows a computational paradigm shift, aimed at fulfilling the need of customizable yet high-performance flexible hardware. Reconfigurable computing fulfills this need by allowing the physical resources of a chip to be adapted to the computational requirements of a specific program, thus achieving higher levels of computing performance. This dissertation evaluates the area requirements for reconfigurable processing, an important yet often disregarded assessment for partial reconfiguration. Common reconfigurable computing approaches today attempt to create custom circuitry in static co-processor accelerators. We instead focused on a new approach that synthesized semi-custom general-purpose processor cores. Each superscalar processor core's execution units can be customized for a particular application, yet the processor retains its standard microprocessor interface. We analyzed the area consumption for these computational components by studying the synthesis requirements of different processor configurations. This area/performance assessment aids designers when constraining processing elements in a fixed-size area slot, a requirement for modern partial reconfiguration approaches. Our results provide a more deterministic evaluation of performance density, hence making the area cost analysis less ambiguous when optimizing dynamic systems for coarse-grained parallelism. The results obtained showed that even though performance density decreases with processor complexity, the additional area still provides a positive contribution to the aggregate parallel processing performance. This evaluation of parallel execution density contributes to ongoing efforts in the field of reconfigurable computing by providing a baseline for area/performance trade-offs for partial reconfiguration and multi-processor systems.
    URI
    http://hdl.handle.net/1808/5670
    Collections
    • Engineering Dissertations and Theses [1055]
    • Dissertations [4473]

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    785-864-8983
    KU Libraries
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    785-864-8983

    KU Libraries
    1425 Jayhawk Blvd
    Lawrence, KS 66045
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    Contact KU ScholarWorks
    785-864-8983
    KU Libraries
    1425 Jayhawk Blvd
    Lawrence, KS 66045
    785-864-8983

    KU Libraries
    1425 Jayhawk Blvd
    Lawrence, KS 66045
    Image Credits
     

     

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