dc.contributor.advisor | Perrins, Erik | |
dc.contributor.author | Werling, Brett William | |
dc.date.accessioned | 2010-07-30T10:45:19Z | |
dc.date.available | 2010-07-30T10:45:19Z | |
dc.date.issued | 2010-06-28 | |
dc.date.submitted | 2010 | |
dc.identifier.other | http://dissertations.umi.com/ku:11034 | |
dc.identifier.uri | http://hdl.handle.net/1808/6460 | |
dc.description.abstract | This thesis outlines the hardware design of a soft output Viterbi algorithm decoder for use in a serially concatenated convolutional code system. Convolutional codes and their related structures are described, as well as the algorithms used to decode them. A decoder design intended for a field-programmable gate array is presented. Simulations of the proposed design are compared with simulations of a software reference decoder that is known to be correct. Results of the simulations are shown and interpreted, and suggestions for future improvements are given. | |
dc.format.extent | 65 pages | |
dc.language.iso | EN | |
dc.publisher | University of Kansas | |
dc.rights | This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author. | |
dc.subject | Computer engineering | |
dc.title | A Hardware Implementation of the Soft Output Viterbi Algorithm for Serially Concatenated Convolutional Codes | |
dc.type | Thesis | |
dc.contributor.cmtemember | Gill, Andrew | |
dc.contributor.cmtemember | Alexander, Perry | |
dc.thesis.degreeDiscipline | Electrical Engineering & Computer Science | |
dc.thesis.degreeLevel | M.S. | |
kusw.oastatus | na | |
kusw.oapolicy | This item does not meet KU Open Access policy criteria. | |
kusw.bibid | 7078882 | |
kusw.bibid | 7078882 | |
dc.rights.accessrights | openAccess | |