A Voltage Controlled Oscillator for a Phase-Locked Loop Frequency Synthesizer in a Silicon-on-Sapphire Process

Abstract

Engineers from a government-owned engineering and manufacturing facility were contracted by government-owned research laboratory to design and build an S-band telemetry transmitter using Radio Frequency Integrated Circuit (RFIC) technology packaged in a Low-Temperature Co-fired Ceramic (LTCC) Multi-Chip Module. The integrated circuit technology chosen for the Phase-Locked Loop Frequency Synthesizer portion of the telemetry transmitter was a 0.25 um CMOS process that utilizes a sapphire substrate and is fabricated by Peregrine Semiconductor corporation. This thesis work details the design of the Voltage Controlled Oscillator (VCO) portion of the PLL frequency synthesizer and constitutes an fully integrated VCO core circuit and a high-isolation buffer amplifier. The high-isolation buffer amplifier was designed to provide 16 dB of gain for 2200-3495 MHz as well as 60 dB of isolation for the oscillator core to provide immunity to frequency pulling due to RF load mismatch. Actual measurements of the amplifier gain and isolation showed the gain was approximately 5 dB lower than the simulated gain when all bond-wire and test substrate parasitics were taken into account. The isolation measurements were shown to be 28 dB at the high end of the frequency band but the measurement was more than likely compromised due to the aforementioned bond-wire and test substrate parasitics. The S-band oscillator discussed in this work was designed to operate over a frequency range of 2200 to 2300 MHz with a minimum output power of 0 dBm with a phase-noise of -92 dBc/Hz at a 100 kHz offset from the carrier. The tuning range was measured to be from 2215 MHz to 2330 MHz with a minimum output power of -7 dBm over the measured frequency range. A phase-noise of -90 dBc was measured at a 100 kHz offset from the carrier.