A New Fault-Tolerant Topology and Operation Scheme for the High Voltage Stage in a Three-Phase Solid-State Transformer

Abstract

Solid-state transformers (SSTs) are comprised of several cascaded power stages with different voltage levels. This leads to more challenges for operation and maintenance of the SSTs not only under critical conditions, but also during normal operation. However, one of the most important reliability concerns for the SSTs is related to high voltage side switch and grid faults. High voltage stress on the switches, together with the fact that most modern SST topologies incorporate large number of power switches in the high voltage side, contribute to a higher probability of a switch fault occurrence. The power electronic switches in the high voltage stage are under very high voltage stress, significantly higher than other SST stages. Therefore, the probability of the switch failures becomes more substantial in this stage. In this research, a new technique is proposed to improve the overall reliability of the SSTs by enhancing the reliability of the high voltage stage.The proposed method restores the normal operation of the SST from the point of view of the load even though the input stage voltages are unbalanced due to the switch faults. On the other hand, high voltage grid faults that result in unbalanced operating conditions in the SST can also lead to dire consequences in regards to safety and reliability. The proposed method can also revamp the faulty operation to the pre-fault conditions in the case of grid faults. The proposed method integrates the quasi-z-source inverter topology into the SST topology for rebalancing the transformer voltages. Therefore, this work develops a new SST topology in conjunction with a fault-tolerant operation strategy that can fully restore operation of the proposed SST in the case of the two aforementioned fault scenarios. The proposed fault-tolerant operation strategy rebalances the line-to-line voltages after a fault occurrence by modifying the phase angles between the phase voltages generated by the high voltage stage of the proposed SST. The boosting property of the quasi z source inverter topology circuitry is then used to increase the amplitude of the rebalanced line-to-line voltages to their pre-fault values. A modified modulation technique is proposed for modifying the phase angles and controlling the quasi z source inverter topology shoot-through duty ratio. The specific contributions of this work are as follows: • The proposed method enables the SST to operate normally in case of switch fault occurrences due to high voltage stress. The function of faulty cells is compensated for without adding any extra legs or backup power cells. The remaining healthy cells are used to modify and balance the output voltage. • Using the proposed method, the delivered power by the SST after fault occurrence will be the same as the pre-fault conditions. Modifying the angles of phase voltages and using the feature of the proposed SST to boost the voltages lead to deliver the same power as in the pre-fault conditions. • Using the quasi-z-source inverter topology in the proposed method increases the reliability of the proposed SST topology since the transformer will have the ability to generate balanced three phase voltages using only two phase voltages. • The proposed method increases the lifetime of the SST after fault occurrence by distributing the voltage stress symmetrically between all cells of the high voltage stage in the three phases . • The proposed method guarantees the regulation of the output voltage of the SST, since the proposed SST topology can isolate the load from any disturbances in the grid. Also, the obtained output voltage of the proposed SST is balanced. As a result of this, there is no difference between the pre-fault voltage and post-fault voltage. Therefore, the obtained voltages will be synchronized well with the grid.