Perrins, ErikRea Zanabria, Gino2011-06-212011-06-212011-03-312011http://dissertations.umi.com/ku:11339https://hdl.handle.net/1808/7644This thesis presents a hardware design of a coherent demodulator for shaped offset quadrature phase shift keying, telemetry group version (SOQPSK-TG) for use in forward error correction (FEC) applications. Implementation details for data sequence detection, symbol timing synchronization, carrier phase synchronization, and block recovery are described. This decision-directed demodulator is based on maximum likelihood principles, and is efficiently implemented by the soft output Viterbi algorithm (SOVA). The design is intended for use in a field-programmable gate array (FPGA). Simulation results of the demodulator's performance in the additive white Gaussian noise channel are compared with a Matlab reference model that is known to be correct. In addition, hardware-specific parameters are presented. Finally, suggestions for future work and improvements are discussed.116 pagesenThis item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.Electrical engineeringDemodulatorFecFpgaHardwareImplementationSoqpsk-tgThesisopenAccess