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A Hardware Implementation of the Soft Output Viterbi Algorithm for Serially Concatenated Convolutional Codes
Werling, Brett William
Werling, Brett William
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Abstract
This thesis outlines the hardware design of a soft output Viterbi algorithm decoder for use in a serially concatenated convolutional code system. Convolutional codes and their related structures are described, as well as the algorithms used to decode them. A decoder design intended for a field-programmable gate array is presented. Simulations of the proposed design are compared with simulations of a software reference decoder that is known to be correct. Results of the simulations are shown and interpreted, and suggestions for future improvements are given.
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Date
2010-06-28
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University of Kansas
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Computer engineering