Fault-Tolerant Space Vector Modulation for Modular Multilevel Converters With Bypassed Faulty Submodules

This paper develops a modulation based fault-tolerant (FT) strategy for restoring the operation of three-phase modular multilevel converters (MMCs) with faulty switches. This FT strategy is based on a proposed modified space vector modulation (SVM) technique that generates balanced line-to-line (line) voltages even in the case of a fault occurrence. In the postfault operation, the proposed strategy is able to restore the fundamental amplitude of the line to the neutral (load) voltages to that of the normal operation condition with a slightly increased voltage stress over the switches in the faulty phase. In this paper, first a brief background about MMCs and SVM technique is provided. Then, the proposed FT strategy and the modified SVM technique are presented. Finally, several simulation and experimental results are provided to validate operation of the proposed strategy.


I. INTRODUCTION
M ODULAR multilevel converters (MMCs) are an attractive solution for applications [1], [2]. They feature superior characteristics, such as high modularity [3], high efficiency [4], higher voltage level availability [5], low total harmonic distortion (THD) [6], and high power quality [7]. However, these admirable aspects come at the price of a more complicated structure with an increased number of power electronic devices. Thus, the chances of fault occurrence increase [8]. High reliability is a critical attribute for the power converters in the industry [9], [10]. Thus, proposing fault-tolerant (FT) methods for multilevels converters (MLC) has been a subject of importance for researchers in the field of power electronics [11]. Recently, several FT control methods have been presented for the MLC, however, only a few of them are suitable for MMCs [8], [12]. In [13], various fault modes of an MMC are discussed. Usually, after detecting the location of the fault, the defective submodules (SMs) are bypassed and an FT strategy is applied [14]. However, this leads to the generation of unbalanced line-to-line (line) voltages. The conventional answer to this problem is to bypass one additional SM in the opposite leg of the faulty phase and two corresponding operative SMs in the healthy phases [15]. This results in balanced operation; however, it renders six SMs nonoperational, resulting in a significant reduction of converter's capacity [16]. To overcome this problem, a number of auxiliary SMs are incorporated in each phase [17]- [19]. In [17], these auxiliary SMs are not engaged in the normal operation of the converter. The main drawback is that the auxiliary SMs' start-up performance suffers from long charging time and transient issues. In [18], a strategy was developed to initiate these SMs during the normal operation by charging their capacitors. It is worth mentioning that the auxiliary SMs used in [18] are not permanently used during the normal operation of the converter. In [20], however, the reserved SMs are often employed. This strategy controls the MMC with some hot redundant SMs based on the carrier based pulsewidth modulation (CB-PWM). All of the SMs work in the operating and standby modes in a specific order.
The MMCs are well-suited for hardware-based techniques due to their modular topology [16]- [19]. However, not much effort is made to modify the modulation technique to exploit some of the inherent merits of MMCs [21]. The works in [22] and [23] are a few examples of FT methods, which modify the modulation. In [23] and [24], FT methods based on the CB-PWM are reported. In these papers, the references are modified to generate balanced phase voltages. In [25], an FT scheme based on fundamental phase compensation (FPSC) PWM is presented. The space vector modulation (SVM) is another widely used modulation technique for MLC [26]. However, there are few studies for MMCs controlled by the SVM [26]- [30]. In [28] and [29], an SVM method with capacitor voltage balancing and circulating current suppression (CCS) is presented; however, the implementation of this method is very complicated. In [27], a dual-SVM method for the MMC is proposed; however, this work does not employ any current suppression and capacitor 0278-0046 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information. voltage control. Another work [30] maximizes the achievable voltage levels, which leads to better control of the capacitor voltage, circulating current, and common-mode voltage reduction. Although researchers have developed some valuable SVM methods for the MMCs, no effort has been made to control the converter in a faulty condition by adopting the SVM technique.
For the other ML topologies however, a few FT strategies based on SVM have been reported [31]- [33]. The strategy proposed in [32], for instance, bypasses the faulty cell and utilizes the redundant switching states via SVM to generate balanced converter voltages. In [33], the idea of FPSC has inspired the authors to define a new space vector diagram for the SVM by introducing a new abc set of axes with arbitrary phase shifts. The purpose of this paper is to propose a new control-based FT strategy for an MMC with bypassed faulty SMs. The proposed FT strategy generates balanced line voltages without employing auxiliary SMs or bypassing any SMs in the healthy phases, makes better use of the converter capacity, and generates line to the neutral (load) voltages with the same fundamental amplitude of normal operation.

A. Modular Multilevel Converter
The circuit topology of the MMC used in this paper is illustrated in [19, Fig. 1]. As pictured, each leg of the MMC is comprised of an upper arm (p) and a lower arm (n), each made up of N SMs. The middle point of the upper and lower arms (V a point in [19, Fig. 1]) is connected to the load. Each arm also incorporates an inductor (L arm ) with an equivalent internal resistance (R arm ). Each SM is comprised of a standard half-bridge and a capacitor (C). The capacitor can be placed in the circuit or bypassed using the half-bridge switches. Accordingly, by labeling the input terminal voltage of each SM as u c , the output terminal voltage of each SM can be made equal to zero (SM is said to be OFF) or u c (SM is said to be ON). In almost all applications, if the voltage drops in the circuit are neglected, the voltage of all SM capacitors are regulated ideally to u c = V dc /N , where N is the number of SMs per arm. Therefore, the upper arm voltages (u pa , u pb , u pc ) and lower arm voltages (u na , u nb , u nc ) can be controlled by controlling the number of ON SMs in each arm. For simplicity, all of the converter voltages are normalized to V dc and the voltage values are given in per unit (p.u.) terms. According to this convention, the voltage levels generated by phases of the converter (0, V dc /N , 2V dc /N, . . . , V dc ) are normalized to 0, 1/N, 2/N, . . . , 1 in p.u. terms.

B. Conventional SVM
The SVM method generates the switching signals based on the instantaneous position of a rotating reference vector in the voltage vector space of the converter. The space vector diagram of the (N + 1)-level converter is illustrated in Fig. 2. Each dot in this figure represents a voltage vector [33]. The voltage vectors are related to converter phase voltages. The relationship in the a-b-c and stationary α-β reference frames is [33] where V ag , V bg , and V cg are the phase voltages of the converter in the a-b-c reference frame and V αg and V β g are the phase voltages in a stationary α-β reference frame. These voltages are related to the switching states (S a , S b , S c ) according to [33] The switching states S a , S b , and S c are defined for the "a," "b," and "c" phases, respectively. Since the voltage levels generated by phases of the converter in p.u. are 0, 1/N, 2/N, . . . , 1, then, according to (2) each switching state has the possible values of 0, 1, 2, . . . , N in order to represent the switching levels. Note that some switching states are redundant meaning that they produce the same vectors. The rotating reference vector is illustrated in [33, Fig. 1] in red color. This vector can be defined as where M is the modulation index and wt is the phase angle of the phase voltages. According to (4), in conventional SVM the reference vector follows a circular path as illustrated in [33, Fig. 1]. The SVM algorithm finds the three nearest voltage vectors to the reference vector ( Fig. 1]) in each step and switches between the three identified voltage vectors during one switching period (T sw ). The amount of time spent at each vector (T x , T y , T z ) is found from [ Finally, SVM algorithm decides on the sequence of switching between the three voltage vectors and chooses one switching state among the redundant states for generating each voltage vector. In this paper, the switching sequence selection is based on generating symmetrical phase voltages for the CCS purposes.

C. Circulating Current Suppression
The circulating current in MMC is caused by the variations of the SM capacitor voltages. These current has almost no effect on ac-side of the MMC and should be suppressed to have a higher efficiency. In [28] and [29], Deng et al. proposed an SVM scheme for MMC that features a CCS method. The following section is a modified adaptation of the CCS method in [28], applied to the (N + 1)-level MMC of [19, Fig. 1]. According to the Kirchhoff's voltage law (KVL), converter's voltage in phase j can be defined as where U p j = u p j /V dc and U nj = u nj /V dc are the upper and lower arm voltages in the p.u. system. From (6) and from [19, where V * j is called the modulation voltage in phase j. By substituting the modulation voltages in (1), the rotating reference of the SVM method can be calculated. Defining I diff ,j = (I p j + I nj )/2, the upper and lower arm currents can be found by adding I ,j /2 to I diff,j and subtracting I ,j /2 from I diff,j . Then, based on KVL, the I diff,j can be calculated by [34] where U diff,j is called the difference voltage of phase j in p.u. system. By controlling this difference voltage in this equation, the I diff,j is restrained in phase j. The circulating current in phase j is I z j = I diff,j -I dc /3. Therefore, to suppress the circulating current in each instant, I diff,j should be driven to I dc / 3. By careful manipulation of the previous relations, we can reach I p,j = I j /2 + I z j + I dc /3, and I n,j = −I j /2 + I z j + I dc /3. On the other hand, the purpose of circulating current control method is to set I z j = 0 by eliminating I z j , I p j = I j /2 + I dc /3 and I nj = -I j /2 + I dc /3. It must be noted that I pj and I nj contain two different ac components (±I j /2) on top of a common dc component (I dc /3). Thus, if the circulating current is successfully eliminated, I pj and I nj will be two currents with the same average value ( I p j = I nj ), and maximum (I pj maximum = I nj maximum ) and minimum (I pj minimum = I nj minimum ) values. Otherwise (if the current suppression method is not employed), these currents will have the same average value but the maximum and minimum values will not be the same anymore. As a result, without the CCS method, the currents in the upper and lower arms will be significantly different. This means that the currents through the capacitors in the lower and upper arms charge the capacitors with different rates; however, the average of the capacitor voltages is still the same. Thus, the FT strategy still can be implemented without the circulation current suppression method: however, the THD quality of the generated waveforms will be negatively affected by the circulating current. In addition, without CCS, the ratings of the MMC components and converter losses are increased significantly [7], [35]. By denoting the number of ON SMs in the upper/lower arms as k p j /k nj , the voltage across the upper arm can be formulated as U p j = k p j /N , while the voltage across the lower arm is U nj = k nj /N . Then, the modulation voltage in (1) and (7) can be rewritten as Moreover, adding U nj = k nj /N to the both sides of (8) yields Thus, the revised number of ON SMs in the upper and lower arms to suppress the circulating current can be calculated from Fig. 1 shows the implementation of (11) for generating the switching voltages in the MMC arms.

D. Voltage Balancing
Once the voltages Vx, Vy, and Vz ([33, Fig. 1]) and the duty cycles dx, dy, and dz are determined by (5), specific set of SMs should be chosen to be turned ON to maintain the voltage balance of the capacitors. The capacitor voltage of SMs and the arm currents can be measured in each sampling time and then a sorting algorithm can be used to choose the proper SMs to be turned ON [2], [35]. In this paper, a sorting algorithm is used for voltage balancing of the MMC [35]. In order to select the proper SM with the highest or lowest voltage, all of the SM voltages in one arm have to be sorted. The basic principles of the voltage-balancing algorithm are as follows [2], [35].
1) According to the generated voltage states (Vx, Vy, and Vz) in the previous part, the number of required ON SMs per the upper and lower arms must be calculated to keep the number of ON SMs equal to N SMs. 2) Considering the arm current direction, during the capacitors charging (or discharging) period the required number of SMs (three in our case) with the lowest (or highest) u c must be ON. The sorting method ensures the capacitor voltages in each arm to be identical. Together with the current control loops, it makes the capacitor voltages of different arms to be also balanced, without requiring large capacitors.

III. PROPOSED FT SVM METHOD
In this section, an SVM-based FT technique for an unbalanced MMC with bypassed SMs is proposed. The proposed SVM technique uses a reformed space vector diagram to generate phase voltages with equal amplitudes that have different number of levels. The reformed space vector diagram for the proposed method is structured according to the modified switching states of the faulty MMC using (1). As mentioned, the voltage levels generated by the converter are 0, 1/N, 2/N, . . . , 1 p.u. In the event of a fault in one of the phases, the defective SM is bypassed using the bidirectional SCR switch between SM terminals A and B (shown in [19, Fig. 1]). In this case, the faulty arm of that phase consists of N − 1 operative SMs, while the healthy arm consists of N operative SMs. In this condition, the faulty phase of the MMC fails to operate as normal condition and cannot generate one of the N feasible voltage levels. The (N − 1) voltage levels in faulty phase along with N voltage levels in healthy phases are substituted in (1) to shape the space vector diagram of the faulty converter. Then, the generated space vector diagram is not symmetric around the faulty phase axis, which results in an asymmetrical phase voltage containing a large undesirable dc-offset component in the faulty phase. Thus, unlike some of the PWM-based FT methods [16], [35], the number of operative SMs in the upper and lower arms must be equal in SVM methods to generate symmetrical waveforms. As a result, one operative SM in the healthy arm must be bypassed. In this condition, the faulty phase is not able to generate all the normal voltage levels (0, 1/N, 2/N, . . . , 1) anymore. As a result, the possible switching states for the faulty phase will be limited to (0, 1/(N − 1), 2/ (N − 1), . . . , 1). To generate the new space vectors, all the possible switching states (S a , S b , and S c ) in the faulty condition are substituted in (2) to find all the possible voltage states (V ag , V bg , and V cg ) in the faulty condition. Then, these voltages are substituted in (1) to find the new space vectors.
For the event of a faulty SM in phases a, b, or c of the MMC, the restructured space vector diagrams created using (1) are shown in Fig. 2(a), (b), and (c), respectively. As illustrated in Fig. 2, the space vector diagrams for the faulty converter no longer resemble the conventional space vector diagram used by traditional SVM algorithms as depicted in [33, Fig. 1].
There are three key distinctions to the new space vector diagrams. First, comparing to the conventional space vectors (dots in [33, Fig. 1]), the location of some new space vectors (dots in Fig. 2) have been altered. This is because fewer voltage levels are generated by the faulty phase of the MMC. Second, since the distances of most of these new space vectors from each other are no longer equal (unlike the conventional MMC), some of the shaped triangles in the new space vector diagrams are not equilateral triangles anymore [the colored triangles in Fig. 2(a)-(c)]. There are some dashed lines in the space vector diagrams of Fig. 2(a)-(c). These dashed lines make-up more nonequilateral triangles that cannot be easily highlighted in Fig. 2 since their positions overlap with colored ones. For example, in Fig. 2(a), one quadrilateral is marked by its four red sides. Two of the triangles within this quadrilateral are colored cyan and light gray. Besides these two triangles, we can imagine two more triangles, which are separated by the dashed line. But, this does not affect the selection of the three nearest vectors to the tip of rotating reference. Indeed, by (5), the three nearest vectors can be calculated in the same procedure. Third, unlike the conventional case, some of the redundant states are mapped to several distinct space vectors. It means for some redundant states, several distinct space vectors are generated using (1). Namely, in Fig. 3(a) that shows a standard space vector diagram for a four-level converter, seven space vectors are identified along the a-axis with dots. Considering the redundancies, 16 switching states exist that could be used to generate these seven space vectors. These switching states are also shown in Fig. 3(a) in parenthesis. However, using (1) to generate new space vectors in faulty phase "a" leads to 11 vectors along the a-axis, identified by dots in Fig. 3(b). The corresponding switching states to the new voltage vectors are also shown in Fig. 3(b) in parenthesis. As illustrated in this figure, each voltage vector is only realizable using one switching state. The number of switching states is reduced from 16 to 12 due to missing voltage level in the faulty phase "a." The external vertices of the hexagonal space vector diagram are shown by the red dots in Fig. 3(a) and (b) for the normal and faulty conditions. As pictured, in the event of a fault, the coordination of these vertices remains the same. Thus, the areas of the two hexagonal space vectors remain equal, which means compared to the healthy MMC, the faulty MMC will be able to deliver the same amount of power to the load. The new path for the rotation of the reference vector is found by transforming the desired three-phase voltages in the faulty condition to the stationary α-β reference frame. Considering the previous example of one bypassed SM per arms in phase "a" for a certain fault scenario, one might assume the amplitude of voltage of phase "a" will be reduced. However, in reality after a transient phase and charging up the SM capacitors, the amplitude of the voltage generated by phase "a" will converge to the same value as the healthy phases but with reduced voltage levels. Therefore, the An abc to α-β transformation is required to transform the set of three-phase voltages in (12) to the stationary α-β reference frame. The standard α-β transformation is used for this purpose ⎡ Substituting (13) in (12) yields the desired voltages in the stationary α-β reference frame which are same as the voltage reference of (4) in a normal converter. This equation describes a circular path in the stationary α-β axes, which is shown in Fig. 3(c) in red. Other than restructuring the space vector diagram, the rest of the modified SVM implementation remains the same as the conventional SVM. As illustrated in Fig. 3(c), the modified SVM algorithm needs to find the three nearest voltage vectors to the reference vector in each step and switch between the three identified voltage vectors during one switching period (T sw ). The amount of time spent at each space vector can be found from (5) similar to conventional SVM. As mentioned previously, by using (1), some of the redundant states generate distinct space vectors for the faulty converter. Consequently, the three identified nearest voltage vectors can be realized each with a unique converter switching state; meaning that the SVM algorithm is no longer required to choose an appropriate switching state among the redundant states for a space vector. In fact, in the proposed method, the state redundancy capacity of the converter is leveraged for the FT operation of the converter to squeeze more voltage vectors along the circular path of the reference vector. Using the proposed method, in some cases, the three nearest voltage vectors no longer shape equilateral triangle. However, the shape of these triangles is not important for calculating the time spent at each of the vector. As mentioned above, the procedure for calculating the time spent at each vector is the same as conventional SVM. In (5), the coordinates of three nearest vectors ( V x , V y , and V z ), which are not necessarily vertices of an equilateral, are used in the coefficients matrix and the coordinates of the reference vector is used in the constant matrix of the system. As long as the reference vector is located inside this triangle, this system of equations has a valid solution that satisfies the practical constraints (0 ≤ T i ≤ T s , i = x, y, z). Additionally, the time spent at each vector can be calculated using the distances of each space vector to the other vectors and the reference vector where A x , A y , and A z are the areas shaped from the distances of V x , V y , and V z to the reference vector. These areas can be seen in Fig. 4. These areas can be easily calculated by using the distances shown in Fig. 4. For example, A x is equal where p is half the perimeter (p = (d x + d y + yz)/2). From this engineering solution, it can be concluded that finding a set of solutions does not depend on the shape of triangle.
Finally, it is worth mentioning that since the space vectors in the faulty MMC lose their inherent redundancies in the vector diagram that is constructed by the modified FT strategy, each of the previously redundant switching states is now mapped to a unique switching vector. This results in more space vectors comparing with the traditional space vectors in the balanced operation of the converter. The more space vectors shape more triangles in the converter's space diagram. As mentioned before, some of these triangles overlap together and this causes the redundancy of triangles. For instance, consider the quadrilateral of the previous example, which is demonstrated with more detail in Fig. 5. In this quadrilateral, four distinct parts are distinguished by four colors. Every single point in any of the parts is located within two overlapping triangles. As an example, if the tip of the rotating reference vector is located in the Δodb, the three nearest vectors to this point shape either Δabd or Δbcd triangles. In this case, by using (5) the exact coordination of three nearest vectors can be found. However, in some cases, the locations of these three vectors are not unique anymore. The red point in Fig. 5 shows an example of this situation. This point is located within Δacd and Δbcd triangles. Thus, the space vectors "c" and "d" are two nearest vectors and the third one can be one of the "a" and "b" vertices. This is because of equal distances of vectors "a" and "b" from the red point. Based on the desired switching strategy, one of these vectors can be selected as the third vector.
At the end of this part, a flowchart for systematic implementation of the proposed method is given in Fig. 6.

IV. INVESTIGATION OF NEW FT STRATEGY
In this section, the performance of the proposed SVM algorithm is evaluated using investigations on two MMCs with different numbers of SMs in each arm. In the first investigation, several simulations have been carried out on a 10-level 3-phase MMC (nine series connected SMs in [19, Fig. 1]). In the second investigation, the proposed fault tolerant strategy is utilized to revamp the performance of a prototype 4-level MMC (N = 3) in the event of a fault in phase "a" (see Fig. 7). In this setup, the dc-side terminal voltage of converter is equal to 400 V and the output terminals of the MMC are connected to the three-phase inductive load. The proposed method is implemented using TMS320F28335 digital signal processor. The parameters of the system under the test are listed in Table I. In the first investigation, the waveforms for the normal operation of the MMC in Fig. 8 are provided to offer a reference for comparison of the results. By comparing the phase voltages in Fig. 8(a), it can be inferred that these voltages are not balanced.   In normal operation, the amplitude of the fundamental component of the converter's phases "a," "b," and "c" are calculated from Fig. 8 as 219.3, 237, and 237 V, respectively. However, all three load and line voltages are 230.8 and 399.8 V, respectively. According to the harmonic spectrum of the load and line voltages, the THDs of the voltages are 6.7% and the phase shifts are 120°. The generated phase voltages of the converter after activating the proposed FT method are shown in Fig. 9. In the postfault condition, due to bypassing of one SM per each arm in phase "a," this phase generates nine voltage levels, while the healthy phases keep generating all ten voltage levels. To verify generation of balanced line voltages in the postfault condition, the line voltages are plotted in Fig. 9(b). Additionally, the load voltages are shown in Fig. 9(c). According to Fig. 9(e)-(g), all three load and line voltages are 399.8 and 230.8 V. According to the harmonic spectrum of the load and line voltages, the THDs of the voltages are slightly increased to 7.1%; however, the phase shifts are exactly 120°. To get a better idea about the converter operation, the load currents in the event of a single faulty phase are given in Fig. 9(d). As pictured, the amplitude of the three waveforms in the postfault operation are equal (10 A) and the phase shifts are exactly 120°. However, the THD of the current is slightly increased from 0.05% to 0.07% due to fault.
In the second investigation, the waveforms for the normal operation of the MMC with three series-connected SMs in each arm are provided in Fig. 10 to provide a reference for comparison. The amplitudes of the fundamental component of the converter's phases "a," "b," and "c" are calculated from Fig. 10 for normal operation as 218.13, 236, and 237 V, respectively. However, all three load and line voltages are 230.8 and 399.9 V, respectively. From analyzing the harmonic spectrums of the waveforms, the THD of the load voltages are 19% and the phase shifts are 120°. The generated phase voltages of the converter after activating the proposed FT method are shown in Fig. 11. In the postfault condition, due to the bypassed SMs in phase "a," this phase generates three voltage levels. According to Fig. 11, however, the amplitude of voltage of phase "a" is still equal to 218 V, although the number of the voltage levels in this phase is reduced. According to harmonic spectrum given in Fig. 11(e)-(g), the amplitudes of the load and line voltages are all equal to 230.8 and 399.8 V, respectively. From analyzing the harmonic spectrums, the THD of the load voltages are 21%, 19%, and 21%, respectively, and the phase shifts are 120°. Again, the load currents in the event of a single faulty phase are given in Fig. 11(d). As pictured, the amplitude of the three waveforms in the postfault operation are equal (10 A) and the  phase shifts are exactly 120°. However, the THD of the current is slightly increased from 1.3% to 1.5% due to fault occurrence.
Finally, Fig. 12 analyzes the operation of the current suppression and voltage balancing methods. According to Fig. 12(f), the circulating currents in phases "a," "b," and "c" are respectively decreased to 10%, 15%, and 20% with the current suppression control. Before applying the CCS method, V * j is not revised based on Section II-C. Thus, the reference is generated regardless of the CCS goal and three nearest vectors are selected. Unlike the PWM methods, the generated phase voltages are different in the SVM method. If the CCS method is not employed, these different voltages result in different amplitudes of circulating currents, particularly, in the faulty phase that includes less operative SMs. Fig. 12(a)-(e) illustrates capacitor voltages of the upper arms and lower arms while the current suppression method is triggered. The rated dc voltage of capacitors in phase "a" of the converter is 200, while these voltages in two other phases are 133 V. By comparing the capacitors voltages of the lower and upper arms, it is observed that the charging and discharging rates are slightly different. This is due to the small circulating currents in the phases of the converter.
Note that the devices must be overdesigned in this approach. However, as the number of SMs increases, the percentage of needed overdesign decreases. For instance, in an MMC with N number of SMs per arm, the rated voltage for the switches and capacitors is 1/N. In the event of a fault, the faulty cell is bypassed and N − 1 SMs remain operative. So, the rated voltage in this case is increased to 1/(N − 1). To find the increment in overdesign ratio we can write Due to these overrated devices, the cost of using the proposed method is different from the conventional solution. In an MMC with a redundant SM for the fault tolerant purposes, the voltage of each SM capacitor is set to V c = 133.3 V. For the safety concerns, the voltage rating of the capacitor is chosen as 1.25 * V c = 166.6 V, as provided in Table II. The voltage rating of the MOSFET is twice the rating of capacitors, equal to 330 V. In this design, each SM includes one voltage sensor, one gate  Each arm contains one inductor and one current sensor. The conventional MMC includes three SMs plus one redundant SM for each arm. Hence, the cost for one arm is 4 × (y 1 + y 2 + y 3 + y 4 + y 5 + 2y 7 + y 11 ) + y 9 + y 10 . In proposed method, if a fault occurs the remaining capacitor and power switches should withstand the dc-link voltage of 400 V. Hence, the voltage of the healthy SM capacitors will be equal to 200 V, and required rating of capacitor voltage is 250 V. This will also cause increment in rating of power switches accordingly. This trend is shown in Table II. The cost for one arm of MMC in the proposed method is 3 × (y 1 + y 2 + y 3 + y 4 + y 6 + 2y 8 + y 11 ) + y 9 + y 10 . By using these two cost functions, a comparison has been performed for the prototype MMC with three SMs per arm. In MMC with one SM redundancy, although the rating of capacitor and power switches are less, but there is a need for four cells. The total cost for one arm in MMC with the conventional solution ($3068) is $512 (20%) more than the cost in the proposed method ($2556).
In addition, the size of the system in the conventional solution is (4/3) 33.3% bigger than the proposed method. Finally, although the cost and size of the MMC converter with proposed method is less, the conventional solution may be preferred in the applications with no cost and size limitation. In these applications, since there is one redundant SM per arm, the proposed method can be employed to revamp the event of the double fault in one phase of the converter.

V. CONCLUSION
In this paper, a new FT strategy based on a modified SVM technique for improving the performance of an MMC converter under faulty conditions was proposed. Using the proposed method, the converter generated balanced line voltages, even with one or more faulty switches. Using the conventional FT strategy, the maximum achievable line voltages for a four-level MMC in the normal and faulty operations were the same. The proposed strategy can easily be implemented on various types of MMCs without limitation on the number of voltage levels.