A Hardware Implementation of the Soft Output Viterbi Algorithm for Serially Concatenated Convolutional Codes
Issue Date
2010-06-28Author
Werling, Brett William
Publisher
University of Kansas
Format
65 pages
Type
Thesis
Degree Level
M.S.
Discipline
Electrical Engineering & Computer Science
Rights
This item is protected by copyright and unless otherwise specified the copyright of this thesis/dissertation is held by the author.
Metadata
Show full item recordAbstract
This thesis outlines the hardware design of a soft output Viterbi algorithm decoder for use in a serially concatenated convolutional code system. Convolutional codes and their related structures are described, as well as the algorithms used to decode them. A decoder design intended for a field-programmable gate array is presented. Simulations of the proposed design are compared with simulations of a software reference decoder that is known to be correct. Results of the simulations are shown and interpreted, and suggestions for future improvements are given.
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- Engineering Dissertations and Theses [1055]
- Theses [3942]
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